1. Field of the Invention
The present invention relates to an analog-digital converter in which a gain can be selected when an analog image signal is converted into a digital image signal and the digital image is output: a solid-state image capturing apparatus using the analog-digital converter to make it possible to capture an image light from a subject; and an electronic information device, such as a digital camera (e.g., a digital video camera, a digital still camera), an image input scanner, a facsimile machine, a cell phone device equipped with a camera and the like, using the solid-state image capturing apparatus as an image input device for an image capturing section.
2. Description of the Related Art
As disclosed in Reference 1, in a solid-state image capturing apparatus, such as a conventional CMOS image sensor, when converting an analog image signal into a digital image signal and being output, an input signal amplifier in an analog-digital converter selects a high gain to make a bright image if the voltage level of an imaging data from a pixel section is too low. Such a conventional image sensor is shown in FIG. 8.
FIG. 8 is a block diagram showing an exemplary essential structure of a conventional CMOS image sensor. Although the actual pixel arrangement has, for example, 1200 rows×1600 columns, for the sake of simplicity, the pixel arrangement which includes a pixel section has four rows and four columns as shown in FIG. 8.
In FIG. 8, a conventional CMOS image sensor 100 includes: a plurality of pixel sections 101, which are arranged in two dimensional matrix; a y-axis decoder 102 for sequentially selecting each row in a pixel arrangement; a plurality of amplifiers (input signal amplifier) 103 for amplifying an output voltage of each column in the pixel arrangement; a plurality of comparators 104 for comparing an input voltage of each amplifier 103 with an analog ramp voltage ARMP (the ramp means a tilt); a digital latch section 105 for storing a digital ramp signal DRMP (multiple bit data) when the input voltage and the analog ramp voltage ARMP from each amplifier 103 are equal; an x-axis decoder 106 for sequentially selecting each column of the pixel arrangement by sequentially selecting latch sections 105 so that a signal is output to a plurality of bit lines; an analog ramp generator 107 for generating the analog ramp voltage ARMP, which is a triangular wave that sequentially increases the voltage level; and a digital ramp generator 108 for generating a digital ramp signal DRMP, in which a digital value sequentially increases in synchronization with the analog ramp voltage ARMP. In addition, a conventional analog-digital converter is configured with the amplifier 103, the comparator 104, the latch section 105, the analog ramp generator 107, and the digital ramp generator 108.
In the conventional CMOS image sensor 100 with the structure described above, an incident light (a subject light) is first photoelectrically converted by each pixel section 101 and is then output as an imaging signal voltage. In the y-axis decoder 102, only one row is selected sequentially from the pixel arrangement in accordance with an inputted address signal YADDR. An output voltage selected from one row of pixel sections 101 is amplified via the corresponding amplifier 103 and is input into a corresponding comparator 104. Each amplifier 103 is a gain selecting section, where, for example, an original gain and a doubled gain are selected in accordance with a selecting signal GSEL, so that the output voltage from each pixel section 101 is amplified.
Subsequently, the analog ramp voltage ARMP and the input voltage are compared with each other in each comparator 104, and when both are equal to each other, the digital ramp signal DRMP, which increases the voltage level in synchronization with the analog ramp voltage ARMP, is stored in the latch section 105. That is, a digital value of a digital ramp signal DRMP, which is at the same voltage level as the analog ramp voltage ARMP, is stored in the latch section 105 when the analog ramp signal DRMP increases and has the same voltage level as the voltage level of the input voltage of the pixel section 101. As a result, the input voltage of the pixel section 101 is said to be analog-digital converted.
In this way, subsequent to the completion of an analog-digital converting operation for one row, each latch section 105 is sequentially selected at the x-axis decoder 106 in accordance with an inputted address signal XADDR, and each latched digital ramp signal DRMP is sequentially output as an analog-digital converting output signal DOUT.
A clock signal CLOCK and a synchronizing signal SYNC are input to the analog ramp generator 107 and the digital ramp generator 108. The analog ramp voltage ARMP, which is gradually increased the voltage level, is generated at the analog ramp generator 107, whereas a digital ramp signal DRMP is generated at the digital ramp generator 108, the digital ramp signal DRMP changing such that the digital ramp signal is increased its voltage level in synchronization with the analog ramp voltage ARMP.
A series of analog-digital converting operations described above are performed for every row in the pixel arrangement, so that the information of a digital image is output as image data.
Reference 1: Japanese Laid-Open Publication No. 2006-50231